Two methods may conventionally be distinguished in the making of vias, more generally employed to make field-effect transistors.
A first method, known as the “subtractive method,” comprises making such vias by physical or chemical attack on the layer or layers of insulation or semi-conducting material to be passed through. This attack is delivered by laser ablation, solvent jet, embossing, or even by the use of a dielectric layer radiation curable under the effect of ultraviolet radiation. It is therefore necessarily made after the insulation or semi-conducting layer has been deposited.
Depending on the architecture used to make field-effect, and in particular “bottom-gate” or “top-gate” transistors, this attack stage occurs at the end of the process or in mid-process.
Such an attack is capable of generating pollutions, and in particular those constituted by fragments caused by the laser shot, solvent residues, as well as by impairments to the semi-conducting layer when the latter is subjected to ultraviolet radiation. Such pollutions prove in fact to be particularly critical when they affect the semi-conductor/insulator interface, and may be severely detrimental to the electrical performance of the transistors. Moreover, the accumulation of steps at the end of the process increases the danger of causing impairment to the layers already deposited, such impairment translating in particular into the disbonding of the layers after laser firing, or even the unintentional dissolution of part of the layers when the vias are made by jets of solvent, etc.
A second method, known as the “selective method,” comprises depositing the insulation or semi-conducting layer selectively. This method comprises locally depositing the insulation or semi-conducting layer while avoiding some zones. In zones that are blank, in other words devoid of insulation or semi-conducting material, the first conducting level, in other words the lower layer of the conducting material, is bare. The blank zones are therefore intended to act as vias. This method has the advantage of not generating pollution of the type described in relation to the previous method.
To make a localized deposition, printing techniques such as flexography, heliography, inkjet, or serigraphy can be used. However, experience shows that the use of some dielectric or semi-conducting materials is difficult to formulate in an ink appropriate for printing techniques. The most straightforward are still full layer deposition using technologies that are well-known to those skilled in the art under the terms “spin coating,” “dip-coating,” “spray coating,” etc. Moreover, these deposition methods do not provide sufficient spatial resolution in a large number of applications.
The objective targeted by the present invention is to make the interconnection vias while eliminating the drawbacks associated with the currently available techniques which have been briefly reviewed above.